Memory cells of a dynamic random access memory (DRAM) comprise a storage capacitor for storing an electrical charge which represents an information to be stored, and an access transistor for addressing the storage capacitor. The access transistor includes a first and a second source/drain regions, a conductive channel adjacent to the first and second source/drain regions as well as a gate electrode controlling an electrical current flowing between the first and second source/drain regions. The transistor usually is formed in a semiconductor substrate. The information stored in the storage capacitor is read out or written in by addressing the access transistor. There is a lower boundary of the channel length of the access transistor, below which the isolation properties of the access transistor in an non-addressed state are not sufficient. The lower boundary of the effective channel length Leff limits the scalability of planar transistor cells having an access transistor which is horizontally formed with respect to the substrate surface of the semiconductor substrate.
Vertical transistor cells offer a possibility of enhancing the channel length while maintaining the surface area necessary for forming the memory cell. In such a vertical transistor cell the source/drain regions of the access transistor as well as the channel region are aligned in a direction perpendicular to the substrate surface. One of the problems involved with such a vertical transistor cell is the difficulty in providing a surface contact to a stacked capacitor. Accordingly, such a vertical transistor is difficult to integrate with a stack capacitor.
A concept, in which the effective channel length Leff is enhanced, refers to a recessed channel transistor, as is for example known from U.S. Pat. No. 5,945,707. In such a transistor, the first and second source/drain regions are arranged in a horizontal plane parallel to the substrate surface. The gate electrode is arranged in a recessed groove, which is disposed between the two source/drain regions of the transistor in the semiconductor substrate. Accordingly, the effective channel length equals to the sum of the distance between the two source/drain regions and the two fold of the depth of the recess groove. The effective channel width Weff corresponds to the minimal structural size F.
Another known transistor concept refers to the FinFET. The active area of a FinFET usually has the shape of a fin or a ridge which is formed in the semiconductor substrate between the two source/drain regions. A gate electrode encloses the fin at two or three sides thereof.
Memory devices usually comprise a memory cell array as well as a peripheral portion. The peripheral portion includes circuitry for operating the memory cell array. With shrinking ground rules for the memory cells a problem arises, that the peripheral portion consumes much space and, in addition, suffers from reliability problems which are for example due to the scaling of the bitline voltage and the wordline voltage. Accordingly, a transistor is desirable, which solves the problems mentioned above and which can as well be used in the peripheral portion of a memory device.